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lm2747 synchronous buck controller with pre-bias startup, and optional clock synchronization general description the lm2747 is a high-speed synchronous buck regulator controller with a feedback voltage accuracy of 1%. it can provide simple down conversion to output voltages as low as 0.6v. though the control section of the ic is rated for 3 to 6v, the driver section is designed to accept input supply rails as high as 14v. the use of adaptive non-overlapping mosfet gate drivers helps avoid potential shoot-through problems while maintaining high efficiency. the ic is designed for the more cost-effective option of driving only n-channel mos- fets in both the high-side and low-side positions. it senses the low-side switch voltage drop for providing a simple, adjustable current limit. the lm2747 features a fixed-frequency voltage-mode pwm control architecture which is adjustable from 50 khz to 1 mhz with one external resistor. in addition, the lm2747 also allows the switching frequency to be synchronized to an external clock signal over the range of 250 khz to 1 mhz. this wide range of switching frequency gives the power supply designer the flexibility to make better tradeoffs be- tween component size, cost and efficiency. features include the ability to startup with a pre-biased load on the output, soft-start, input undervoltage lockout (uvlo) and power good (based on both undervoltage and overvolt- age detection). in addition, the shutdown pin of the ic can be used for providing startup delay, and the soft-start pin can be used for implementing precise tracking, for the purpose of sequencing with respect to an external rail. features n 1% feedback voltage accuracy over temperature n switching frequency from 50 khz to 1 mhz n switching frequency synchronize range 250 khz to 1 mhz n startup with a pre-biased output load n power stage input voltage from 1v to 14v n control stage input voltage from 3v to 6v n output voltage adjustable down to 0.6v n power good flag and shutdown n output overvoltage and undervoltage detection n low-side adjustable current sensing n adjustable soft-start n tracking and sequencing with shutdown and soft start pins n tssop-14 package applications n down conversion from 3.3v n cable modem, dsl and adsl n laser jet and ink jet printers n low voltage power modules n dsp, asic, core and i/o typical application 20150901 march 2006 lm2747 synchronous buck controller with pre-bias startup, and optional clock synchronization ? 2006 national semiconductor corporation ds201509 www.national.com
connection diagram 20150990 14-lead plastic tssop ja = 155?c/w ns package number mtc14 ordering information order number package type nsc package drawing supplied as lm2747mtc tssop-14 mtc14 94 units on rail lm2747mtcx 2500 units on tape and reel pin description boot (pin 1) - bootstrap pin. this is the supply rail for the high-side gate driver. when the high-side mosfet turns on, the voltage on this pin should be at least one gate threshold above the regulator input voltage v in to properly turn on the mosfet. see mosfet gate drivers in the application information section for more details on how to select mos- fets. lg (pin 2) - low-gate drive pin. this is the gate drive for the low-side n-channel mosfet. this signal is interlocked with the high-side gate drive hg (pin 14), so as to avoid shoot- through. pgnd (pins 3, 13) - power ground. this is also the ground for the low-side mosfet driver. both the pins must be connected together on the pcb and form a ground plane, which is usually also the system ground. sgnd (pin 4) - signal ground. it should be connected appropriately to the ground plane with due regard to good layout practices in switching power regulator circuits. v cc (pin 5) supply rail for the control sections of the ic. pwgd (pin 6) - power good pin. this is an open drain output, which is typically meant to be connected to v cc or any other low voltage source through a pull-up resistor. choose the pull-up resistor so that the current going into this pin is kept below 1 ma. a recommended value for the pull-up resistor is 100 k ? for most applications. the voltage on this pin is thus pulled low under output undervoltage or overvolt- age fault conditions and also under input uvlo. i sen (pin 7) - current limit threshold setting pin. this sources a fixed 40 a current. a resistor of appropriate value should be connected between this pin and the drain of the low-side mosfet (switch node). the minimum value for this resistor is1k ? . eao (pin 8) - output of the error amplifier. the voltage level on this pin is compared with an internally generated ramp signal to determine the duty cycle. this pin is necessary for compensating the control loop. ss/track (pin 9) - soft-start and tracking pin. this pin is internally connected to the non-inverting input of the error amplifier during soft-start, and in fact any time the ss/ track pin voltage happens to be below the internal refer- ence voltage. for the basic soft-start function, a capacitor of minimum value 1 nf is connected from this pin to ground. to track the rising ramp of another power supply?s output, con- nect a resistor divider from the output of that supply to this pin as described in application information. fb (pin 10) - feedback pin. this is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating the control loop. freq/sync (pin 11) - frequency adjust pin. the switching frequency is set by connecting a resistor of suitable value between this pin and ground. some typical values (rounded up to the nearest standard values) are 150 k ? for 200 khz, 100 k ? for 300 khz, 51.1 k ? for 500 khz, 18.7 k ? for 1 mhz. this pin is also used to synchronize to an external clock within the range of 250khz to 1mhz. sd (pin 12) - ic shutdown pin. pull this pin to v cc to ensure the ic is enabled. connect to ground to disable the ic. under shutdown, both high-side and low-side drives are off. this pin also features a precision threshold for power supply sequencing purposes, as well as a low threshold to ensure minimal quiescent current. hg (pin 14) - high-gate drive pin. this is the gate drive for the high-side n-channel mosfet. this signal is interlocked with lg (pin 2) to avoid shoot-through. lm2747 www.national.com 2
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. v cc -0.3 to 7v boot voltage -0.3 to 18v i sen -0.3 to 14v freq/sync voltage -0.5 to v cc + 0.3v all other pins -0.3 to v cc + 0.3v junction temperature 150?c storage temperature ?65?c to 150?c soldering information lead temperature (soldering, 10sec) 260?c infrared or convection (20sec) 235?c esd rating (note 3) 2kv operating ratings supply voltage range, v cc (note 2) 3v to 6v boot voltage range 1v to 17v junction temperature range (t j ) ?40?c to +125?c thermal resistance ( ja ) 155?c/w electrical characteristics v cc = 3.3v unless otherwise indicated. typicals and limits appearing in plain type apply for t a =t j = 25?c. limits appearing in boldface type apply over full operating temperature range. datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. symbol parameter conditions min typ max units v fb fb pin voltage v cc =3vto6v 0.594 0.6 0.606 v v on uvlo thresholds v cc rising v cc falling 2.79 2.42 v i q_vcc operating v cc current v cc = 3.3v, v sd = 3.3v f sw = 600 khz 1.1 1.7 2.3 ma v cc = 5v, v sd = 3.3v f sw = 600 khz 1.3 2 2.6 shutdown v cc current v cc = 3.3v, v sd =0v 1 3 a t pwgd1 pwgd pin response time v fb rising 10 s t pwgd2 pwgd pin response time v fb falling 10 s i ss-on ss pin source current v ss =0v 7 10 14 a i ss-oc ss pin sink current during over current v ss = 2.0v 90 a i sen-th i sen pin source current trip point 25 40 55 a i fb fb pin current sourcing 20 na error amplifier gbw error amplifier unity gain bandwidth 9 mhz g error amplifier dc gain 118 db sr error amplifier slew rate 2 v/s i eao eao pin current sourcing and sinking capability 14 16 ma v eao error amplifier output voltage minimum 1 v maximum 2.2 v lm2747 www.national.com 3
electrical characteristics (continued) v cc = 3.3v unless otherwise indicated. typicals and limits appearing in plain type apply for t a =t j = 25?c. limits appearing in boldface type apply over full operating temperature range. datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. symbol parameter conditions min typ max units gate drive i q-boot boot pin quiescent current v boot = 12v, v sd =0 18 90 a r hg_up high-side mosfet driver pull-up on resistance v boot =5v @ 350 ma sourcing 2.7 ? r hg_dn high-side mosfet driver pull-down on resistance 350 ma sinking 0.8 ? r lg_up low-side mosfet driver pull-up on resistance v boot =5v @ 350 ma sourcing 2.7 ? r lg_dn low-side mosfet driver pull-down on resistance 350 ma sinking 0.8 ? oscillator f sw pwm frequency r fadj = 750 k ? 50 khz r fadj = 100 k ? 300 r fadj = 42.2 k ? 475 600 725 r fadj = 18.7 k ? 1000 external synchronizing signal frequency voltage swing = 0v to v cc 250 1000 sync l synchronization signal low threshold f sw = 250 khz to 1 mhz 1 v sync h synchronization signal high threshold f sw = 250 khz to 1 mhz 2 v d max max high-side duty cycle f sw = 300 khz f sw = 600 khz f sw = 1 mhz 86 78 67 % logic inputs and outputs v stby-ih standby high trip point v fb = 0.575v, v boot = 3.3v v sd rising 1.1 v v stby-il standby low trip point v fb = 0.575v, v boot = 3.3v v sd falling 0.232 v v sd-ih sd pin logic high trip point v sd rising 1.3 v v sd-il sd pin logic low trip point v sd falling 0.8 v v pwgd-th-lo pwgd pin trip points v fb falling 0.408 0.434 0.457 v v pwgd-th-hi pwgd pin trip points v fb rising 0.677 0.710 0.742 v v pwgd-hys pwgd hysteresis v fb falling v fb rising 60 90 mv note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device operates correctly. operating ratings do not imply guaranteed performance limits. note 2: the power mosfets can run on a separate 1v to 14v rail (input voltage, v in ). practical lower limit of v in depends on selection of the external mosfet. see the mosfet gate drivers section under application information for further details. note 3: esd using the human body model which is a 100pf capacitor discharged through a 1.5 k ? resistor into each pin. lm2747 www.national.com 4
typical performance characteristics efficiency (v out = 1.2v) v cc = 3.3v, f sw = 1 mhz internal reference voltage vs temperature 20150940 20150958 frequency vs temperature output voltage vs output current 20150960 20150956 switch waveforms v cc = 3.3v, v in = 5v, v out = 1.2v i out = 3a, c ss = 12 nf, f sw = 1 mhz start-up (full-load) v cc = 3.3v, v in = 5v, v out = 1.2v i out = 3a, c ss = 12 nf, f sw = 1 mhz 20150946 20150948 lm2747 www.national.com 5
typical performance characteristics (continued) start-up (no-load) v cc = 3.3v, v in = 5v, v out = 1.2v c ss = 12 nf, f sw = 1 mhz shutdown (full-load) v cc = 3.3v, v in = 5v, v out = 1.2v i out = 3a, c ss = 12 nf, f sw = 1 mhz 20150949 20150950 load transient response v cc = 3.3v, v in = 14v, v out = 1.2v f sw = 1 mhz line transient response (v in =3vto9v) v cc = 3.3v, v out = 1.2v i out = 2a, f sw = 1 mhz 20150953 20150954 frequency vs. frequency adjust resistor maximum duty cycle vs frequency v cc = 3.3v 20150955 20150992 lm2747 www.national.com 6
typical performance characteristics (continued) maximum duty cycle vs v cc f sw = 600 khz maximum duty cycle vs v cc f sw = 1 mhz 20150993 20150994 lm2747 www.national.com 7
block diagram 20150903 application information the lm2747 is a voltage-mode, high-speed synchronous buck regulator with a pwm control scheme. it is designed for use in set-top boxes, thin clients, dsl/cable modems, and other applications that require high efficiency buck convert- ers. it has output shutdown (sd), input undervoltage lock-out (uvlo) mode and power good (pwgd) flag (based on overvoltage and undervoltage detection). the overvoltage and undervoltage signals are or-gated to drive the power good signal and provide a logic signal to the system if the output voltage goes out of regulation. current limit is achieved by sensing the voltage v ds across the low side mosfet. the lm2747 is also able to start-up with the output pre-biased with a load and allows for the switching frequency to be synchronized with an external clock source. start up/soft-start when v cc exceeds 2.79v and the shutdown pin (sd) sees a logic high, the soft-start period begins. then an internal, fixed 10 a source begins charging the soft-start capacitor. during soft-start the voltage on the soft-start capacitor c ss is connected internally to the non-inverting input of the error amplifier. the soft-start period lasts until the voltage on the soft-start capacitor exceeds the lm2747 reference voltage of 0.6v. at this point the reference voltage takes over at the non-inverting error amplifier input. the capacitance of c ss determines the length of the soft-start period, and can be approximated by: where c ss is in f and t ss is in ms. during soft start the power good flag is forced low and it is released when the fb pin voltage reaches 70% of 0.6v. at this point the chip enters normal operation mode, and the output overvoltage and undervoltage monitoring starts. setting the output voltage the lm2747 regulates the output voltage by controlling the duty cycle of the high side and low side mosfets (see typical application circuit).the equation governing output voltage is: setting the switching frequency during fixed-frequency mode of operation the pwm fre- quency is adjustable between 50 khz and 1 mhz and is set by an external resistor, r fadj , between the freq/sync pin and ground. the resistance needed for a desired frequency lm2747 www.national.com 8
application information (continued) is approximated by the curve frequency vs. fre- quency adjust resistor in the typical performance characteristics section. when it is desired to synchronize the switching frequency with an external clock source, the lm2747 has the unique ability to synchronize from this external source within the range of 250 khz to 1 mhz. the external clock signal should be ac coupled to the freq/sync pin as shown below in figure 1 , where the r fadj is chosen so that the fixed fre- quency is approximately within 30% of the external syn- chronizing clock frequency. an internal protection diode clamps the low level of the synchronizing signal to approxi- mately -0.5v. the internal clock synchrinizes to the rising edge of the external clock. it is recommended to choose an ac coupling capacitance in the range of 50 pf to 100 pf. exceeding the recommended capacitance may inject excessive energy through the inter- nal clamping diode structure present on the freq/sync pin. the typical trip level of the synchronization pin is 1.5v. to ensure proper synchronization and to avoid damaging the ic, the peak-to-peak value (amplitude) should be between 2.5v and v cc . the minimum width of this pulse must be greater than 100 ns, and it?s maximum width must be 100ns less than the period of the switching cycle. the external clock synchronization process begins once the lm2747 is enabled and an external clock signal is detected. during the external clock synchronization process the inter- nal clock initially switches at approximately 1.5 mhz and decreases until it has matched the external clock?s fre- quency. the lock-in period is approximately 30 s if the external clock is switching at 1 mhz, and about 100 s if the external clock is at 200 khz. when there is no clock signal present, the lm2747 enters into fixed-frequency mode and begins switching at the frequency set by the r fadj resistor. if the external clock signal is removed after frequency syn- chronization, the lm2747 will enter fixed-frequency mode within two clock cycles. if the external clock is removed within the 30 s lock-in period, the lm2747 will re-enter fixed-frequency mode within two internal clock cycles after the lock-in period. output pre-bias startup if there is a pre-biased load on the output of the lm2747 during startup, the ic will disable switching of the low-side mosfet and monitor the sw node voltage during the off- time of the high-side mosfet. there is no load current sensing while in pre-bias mode because the low-side mos- fet never turns on. the ic will remain in this pre-bias mode until it sees the sw node stays below 0v during the entire high-side mosfet?s off-time. once it is determined that the sw node remained below 0v during the high-side off-time, the low-side mosfet begins switching during the next switching cycle. figure 2 shows the sw node, hg, and lg signals during pre-bias startup. the pre-biased output volt- age should not exceed v cc +v gs of the external high-side mosfet to ensure that the high-side mosfet will be able to switch during startup. tracking a voltage level the lm2747 can track the output of a master power supply during soft-start by connecting a resistor divider to the ss/ track pin. in this way, the output voltage slew rate of the lm2747 will be controlled by the master supply for loads that require precise sequencing. when the tracking function is used no soft-start capacitor should be connected to the ss/track pin. however in all other cases, a c ss value of at least 1 nf between the soft-start pin and ground should be used. one way to use the tracking feature is to design the tracking resistor divider so that the master supply?s output voltage (v out1 ) and the lm2747?s output voltage (represented sym- bolically in figure 3 as v out2 , i.e. without explicitly showing the power components) both rise together and reach their 20150989 figure 1. ac coupled clock 20150991 figure 2. output pre-bias mode waveforms 20150907 figure 3. tracking circuit lm2747 www.national.com 9
application information (continued) target values at the same time. for this case, the equation governing the values of the tracking divider resistors r t1 and r t2 is: the current through r t1 should be about 4 ma for precise tracking. the final voltage of the ss/track pin should be set higher than the feedback voltage of 0.6v (say about 0.65v as in the above equation). if the master supply voltage was 5v and the lm2747 output voltage was 1.8v, for ex- ample, then the value of r t1 needed to give the two supplies identical soft-start times would be 150 ? . a timing diagram for the equal soft-start time case is shown in figure 4 . tracking a voltage slew rate the tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather to have similar rise rates (in terms of output dv/dt). this method ensures that the output voltage of the lm2747 al- ways reaches regulation before the output voltage of the master supply. in this case, the tracking resistors can be determined based on the following equation: for the example case of v out1 = 5v and v out2 = 1.8v, with r t1 set to 150 ? as before, r t2 is calculated from the above equation to be 265 ? . a timing diagram for the case of equal slew rates is shown in figure 5 . sequencing the start up/soft-start of the lm2747 can be delayed for the purpose of sequencing by connecting a resistor divider from the output of a master power supply to the sd pin, as shown in figure 6 . a desired delay time t delay between the startup of the master supply output voltage and the lm2747 output voltage can be set based on the sd pin low-to-high threshold v sd-ih and the slew rate of the voltage at the sd pin, sr sd : t delay =v sd-ih /sr sd note again, that in figure 6 , the lm2747?s output voltage has been represented symbolically as v out2 , i.e. without explicitly showing the power components. v sd-ih is typically 1.08v and sr sd is the slew rate of the sd pin voltage. the values of the sequencing divider resistors r s1 and r s2 set the sr sd based on the master supply output voltage slew rate, sr out1 , using the following equa- tion: 20150908 figure 4. tracking with equal soft-start time 20150910 figure 5. tracking with equal slew rates 20150914 figure 6. sequencing circuit lm2747 www.national.com 10
application information (continued) for example, if the master supply output voltage slew rate was 1v/ms and the desired delay time between the startup of the master supply and lm2747 output voltage was 5 ms, then the desired sd pin slew rate would be (1.08v/5 ms) = 0.216v/ms. due to the internal impedance of the sd pin, the maximum recommended value for r s2 is1k ? . to achieve the desired slew rate, r s1 would then be 274 ? . a timing diagram for this example is shown in figure 7 . sd pin impedance when connecting a resistor divider to the sd pin of the lm2747 some care has to be taken. once the sd voltage goes above v sd-ih , a 17 a pull-up current is activated as shown in figure 8 . this current is used to create the internal hysteresis ( ) 170 mv); however, high external impedances will affect the sd pin logic thresholds as well. the external impedance used for the sequencing divider network should preferably be a small fraction of the impedance of the sd pin for good performance (around 1 k ? ). mosfet gate drivers the lm2747 has two gate drivers designed for driving n-channel mosfets in a synchronous mode. note that unlike most other synchronous controllers, the bootstrap capacitor of the lm2747 provides power not only to the driver of the upper mosfet, but the lower mosfet driver too (both drivers are ground referenced, i.e. no floating driver). two things must be kept in mind here. first, the boot pin has an absolute maximum rating of 18v. this must never be exceeded, even momentarily. since the bootstrap capacitor is connected to the sw node, the peak voltage impressed on the boot pin is the sum of the input voltage (v in ) plus the voltage across the bootstrap capacitor (ignoring any forward drop across the bootstrap diode). the bootstrap capacitor is charged up by a given rail (called v boot_dc here) whenever the upper mosfet turns off. this rail can be the same as v cc or it can be any external ground-referenced dc rail. but care has to be exercised when choosing this bootstrap dc rail that the boot pin is not damaged. for example, if the desired maximum v in is 14v, and v boot_dc is chosen to be the same as v cc , then clearly if the v cc rail is 6v, the peak voltage on the boot pin is 14v + 6v = 20v. this is unac- ceptable, as it is in excess of the rating of the boot pin. a v cc of 3v would be acceptable in this case. or the v in range must be reduced accordingly. there is also the option of deriving the bootstrap dc rail from another 3v external rail, independent of v cc . the second thing to be kept in mind here is that the output of the low-side driver swings between the bootstrap dc rail level of v boot_dc and ground, whereas the output of the high-side driver swings between v in +v boot_dc and ground. to keep the high-side mosfet fully on when de- sired, the gate pin voltage of the mosfet must be higher than its instantaneous source pin voltage by an amount equal to the ?miller plateau?. it can be shown that this plateau is equal to the threshold voltage of the chosen mosfet plus a small amount equal to io/g. here io is the maximum load current of the application, and g is the transconductance of this mosfet (typically about 100 for logic-level devices). that means we must choose v boot_dc to at least exceed 20150911 figure 7. delay for sequencing 20150906 figure 8. sd pin logic lm2747 www.national.com 11
application information (continued) the miller plateau level. this may therefore affect the choice of the threshold voltage of the external mosfets, and that in turn may depend on the chosen v boot_dc rail. so far, in the discussion above, the forward drop across the bootstrap diode has been ignored. but since that does affect the output of the driver somewhat, it is a good idea to include this drop in the following examples. looking at the typical application schematic, this means that the difference voltage v cc -v d1 , which is the voltage the bootstrap capacitor charges up to, must always be greater than the maximum tolerance limit of the threshold voltage of the upper mos- fet. here v d1 is the forward voltage drop across the boot- strap diode d1. this may place restrictions on the minimum input voltage and/or type of mosfet used. a basic bootstrap circuit can be built using one schottky diode and a small capacitor, as shown in figure 9 . the capacitor c boot serves to maintain enough voltage between the top mosfet gate and source to control the device even when the top mosfet is on and its source has risen up to the input voltage level. the charge pump circuitry is fed from v cc , which can operate over a range from 3.0v to 6.0v. using this basic method the voltage applied to the gates of both high-side and low-side mosfets is v cc -v d . this method works well when v cc is 5v 10%, because the gate drives will get at least 4.0v of drive voltage during the worst case of v cc-min = 4.5v and v d-max = 0.5v. logic level mosfets generally specify their on-resistance at v gs = 4.5v. when v cc = 3.3v 10%, the gate drive at worst case could go as low as 2.5v. logic level mosfets are not guaranteed to turn on, or may have much higher on- resistance at 2.5v. sub-logic level mosfets, usually speci- fied at v gs = 2.5v, will work, but are more expensive, and tend to have higher on-resistance. the circuit in figure 9 works well for input voltages ranging from 1v up to 14v and v cc =5v 10%, because the drive voltage depends only on v cc . note that the lm2747 can be paired with a low cost linear regulator like the lm78l05 to run from a single input rail between 6.0 and 14v. the 5v output of the linear regulator powers both the v cc and the bootstrap circuit, providing efficient drive for logic level mosfets. an example of this circuit is shown in figure 10 . figure 11 shows a second possibility for bootstrapping the mosfet drives using a doubler. this circuit provides an equal voltage drive of v cc -3v d +v in to both the high-side and low-side mosfet drives. this method should only be used in circuits that use 3.3v for both v cc and v in . even with v in =v cc = 3.0v (10% lower tolerance on 3.3v) and v d = 0.5v both high-side and low-side gates will have at least 4.5v of drive. the power dissipation of the gate drive cir- cuitry is directly proportional to gate drive voltage, hence the thermal limits of the lm2747 ic will quickly be reached if this circuit is used with v cc or v in voltages over 5v. all the gate drive circuits shown in the above figures typically use 100 nf ceramic capacitors in the bootstrap locations. 20150912 figure 9. basic charge pump (bootstrap) 20150913 figure 10. lm78l05 feeding basic charge pump 20150919 figure 11. charge pump with added gate drive lm2747 www.national.com 12
application information (continued) power good signal the open drain output on the power good pin needs a pull-up resistor to a low voltage source. the pull-up resistor should be chosen so that the current going into the power good pin is less than 1 ma. a 100 k ? resistor is recom- mended for most applications. the power good signal is an or-gated flag which takes into account both output overvoltage and undervoltage condi- tions. if the feedback pin (fb) voltage is 18% above its nominal value (118% x v fb = 0.708v) or falls 28% below that value (72% x v fb = 0.42v) the power good flag goes low. the power good flag can be used to signal other circuits that the output voltage has fallen out of regulation, however the switching of the lm2747 continues regardless of the state of the power good signal. the power good flag will return to logic high whenever the feedback pin voltage is between 72% and 118% of 0.6v. uvlo the 2.79v turn-on threshold on v cc has a built in hysteresis of about 300 mv. if v cc drops below 2.42v, the chip defi- nitely enters uvlo mode. uvlo consists of turning off the top and bottom mosfets and remaining in that condition until v cc rises above 2.79v. as with normal shutdown initi- ated by the sd pin, the soft-start capacitor is discharged through an internal mosfet, ensuring that the next start-up will be controlled by the soft-start circuitry. current limit current limit is realized by sensing the voltage across the low-side mosfet while it is on. the r dson of the mosfet is a known value; hence the current through the mosfet can be determined as: v ds =i out xr dson the current through the low-side mosfet while it is on is also the falling portion of the inductor current. the current limit threshold is determined by an external resistor, r cs , connected between the switching node and the i sen pin. a constant current (i sen-th ) of 40 a typical is forced through r cs , causing a fixed voltage drop. this fixed voltage is compared against v ds and if the latter is higher, the current limit of the chip has been reached. to obtain a more accurate value for r cs you must consider the operating values of r dson and i sen-th at their operating temperatures in your application and the effect of slight parameter differences from part to part. r cs can be found by using the following equation using the r dson value of the low side mosfet at it?s expected hot temperature and the absolute minimum value expected over the full temperature range for the for the i sen-th which is 25 a: r cs =r dson-hot xi lim /i sen-th for example, a conservative 15a current limit in a 10a design with a r dson-hot of 10 m ? would requir ea6k ? resistor. the minimum value for r cs in any application is 1 k ? . because current sensing is done across the low-side mosfet, no minimum high-side on-time is necessary. the lm2747 enters current limit mode if the inductor current exceeds the current limit threshold at the point where the high-side mosfet turns off and the low-side mosfet turns on. (the point of peak inductor current, see figure 12 ). note that in normal operation mode the high-side mosfet al- ways turns on at the beginning of a clock cycle. in current limit mode, by contrast, the high-side mosfet on-pulse is skipped. this causes inductor current to fall. unlike a normal operation switching cycle, however, in a current limit mode switching cycle the high-side mosfet will turn on as soon as inductor current has fallen to the current limit threshold. the lm2747 will continue to skip high-side mosfet pulses until the inductor current peak is below the current limit threshold, at which point the system resumes normal opera- tion. unlike a high-side mosfet current sensing scheme, which limits the peaks of inductor current, low-side current sensing is only allowed to limit the current during the converter off-time, when inductor current is falling. therefore in a typi- cal current limit plot the valleys are normally well defined, but the peaks are variable, according to the duty cycle. the pwm error amplifier and comparator control the off-pulse of the high-side mosfet, even during current limit mode, meaning that peak inductor current can exceed the current limit threshold. assuming that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be calculated with the following equation: where t sw is the inverse of switching frequency f sw . the 200 ns term represents the minimum off-time of the duty cycle, which ensures enough time for correct operation of the current sensing circuitry. in order to minimize the time period in which peak inductor current exceeds the current limit threshold, the ic also dis- charges the soft-start capacitor through a fixed 90 a sink. the output of the lm2747 internal error amplifier is limited by the voltage on the soft-start capacitor. hence, discharging the soft-start capacitor reduces the maximum duty cycle d of the controller. during severe current limit this reduction in duty cycle will reduce the output voltage if the current limit conditions last for an extended time. output inductor current 20150988 figure 12. current limit threshold lm2747 www.national.com 13
application information (continued) will be reduced in turn to a flat level equal to the current limit threshold. the third benefit of the soft-start capacitor dis- charge is a smooth, controlled ramp of output voltage when the current limit condition is cleared. shutdown if the shutdown pin is pulled low, (below 0.8v) the lm2747 enters shutdown mode, and discharges the soft-start capaci- tor through a mosfet switch. the high and low-side mos- fets are turned off. the lm2747 remains in this state as long as v sd sees a logic low (see the electrical character- istics table). to assure proper ic start-up the shutdown pin should not be left floating. for normal operation this pin should be connected directly to v cc or to another voltage between 1.3v to v cc (see the electrical characteristics table). design considerations the following is a design procedure for all the components needed to create the typical application circuit shown on the front page. this design converts 3.3v (v in ) to 1.2v (v out ) at a maximum load of 4a with an efficiency of 89% and a switching frequency of 300 khz. the same procedures can be followed to create many other designs with varying input voltages, output voltages, and load currents. input capacitor the input capacitors in a buck converter are subjected to high stress due to the input current trapezoidal waveform. input capacitors are selected for their ripple current capabil- ity and their ability to withstand the heat generated since that ripple current passes through their esr. input rms ripple current is approximately: where duty cycl ed=v out /v in . the power dissipated by each input capacitor is: where n is the number of paralleled capacitors, and esr is the equivalent series resistance of each capacitor. the equa- tion above indicates that power loss in each capacitor de- creases rapidly as the number of input capacitors increases. the worst-case ripple for a buck converter occurs during full load and when the duty cycle (d) is 0.5. for this 3.3v to 1.2v design the duty cycle is 0.364. for a 4a maximum load the ripple current is 1.92a. output inductor the output inductor forms the first half of the power stage in a buck converter. it is responsible for smoothing the square wave created by the switching action and for controlling the output current ripple ( ? i out ). the inductance is chosen by selecting between tradeoffs in efficiency and response time. the smaller the output inductor, the more quickly the con- verter can respond to transients in the load current. how- ever, as shown in the efficiency calculations, a smaller in- ductor requires a higher switching frequency to maintain the same level of output current ripple. an increase in frequency can mean increasing loss in the mosfets due to the charg- ing and discharging of the gates. generally the switching frequency is chosen so that conduction loss outweighs switching loss. the equation for output inductor selection is: l = 1.6 h here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency, and as- sumed a 40% peak-to-peak output current ripple. this yields an inductance of 1.6 h. the output inductor must be rated to handle the peak current (also equal to the peak switch current), which is (i out + (0.5 x ? i out )) = 4.8a, for a 4a design. the coilcraft do3316p-222p is 2.2 h, is rated to 7.4a peak, and has a direct current resistance (dcr) of 12 m ? . after selecting the coilcraft do3316p-222p for the output inductor, actual inductor current ripple should be re- calculated with the selected inductance value, as this infor- mation is needed to select the output capacitor. re- arranging the equation used to select inductance yields the following: v in(max) is assumed to be 10% above the steady state input voltage, or 3.6v at v in = 3.3v. the re-calculated current ripple will then be 1.2a. this gives a peak inductor/switch current will be 4.6a. output capacitor the output capacitor forms the second half of the power stage of a buck switching converter. it is used to control the output voltage ripple ( ? v out ) and to supply load current during fast load transients. in this example the output current is 4a and the expected type of capacitor is an aluminum electrolytic, as with the input capacitors. other possibilities include ceramic, tanta- lum, and solid electrolyte capacitors, however the ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums tend to be more expensive than aluminum electrolytic. aluminum ca- pacitors tend to have very high capacitance and fairly low esr, meaning that the esr zero, which affects system stability, will be much lower than the switching frequency. the large capacitance means that at the switching fre- quency, the esr is dominant, hence the type and number of output capacitors is selected on the basis of esr. one simple formula to find the maximum esr based on the desired output voltage ripple, ? v out and the designed out- put current ripple, ? i out , is: lm2747 www.national.com 14
application information (continued) in this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor cur- rent ripple, the required maximum esr is 20 m ? . the sanyo 4sp560m electrolytic capacitor will give an equivalent esr of 14 m ? . the capacitance of 560 f is enough to supply energy even to meet severe load transient demands. mosfets selection of the power mosfets is governed by a trade-off between cost, size, and efficiency. one method is to deter- mine the maximum cost that can be endured, and then select the most efficient device that fits that price. breaking down the losses in the high-side and low-side mosfets and then creating spreadsheets is one way to determine relative efficiencies between different mosfets. good correlation between the prediction and the bench result is not guaran- teed, however. single-channel buck regulators that use a controller ic and discrete mosfets tend to be most efficient for output currents of 2 to 10a. losses in the high-side mosfet can be broken down into conduction loss, gate charging loss, and switching loss. conduction, or i 2 r loss, is approximately: p c =d(i o 2 xr dson-hi x 1.3) (high-side mosfet) p c =(1-d)x(i o 2 xr dson-lo x 1.3) (low-side mosfet) in the above equations the factor 1.3 accounts for the in- crease in mosfet r dson due to heating. alternatively, the 1.3 can be ignored and the r dson of the mosfet estimated using the r dson vs. temperature curves in the mosfet datasheets. gate charging loss results from the current driving the gate capacitance of the power mosfets, and is approximated as: p gc =nx(v dd )xq g xf sw where ?n? is the number of mosfets (if multiple devices have been placed in parallel), v dd is the driving voltage (see mosfet gate drivers section) and q gs is the gate charge of the mosfet. if different types of mosfets are used, the ?n? term can be ignored and their gate charges simply summed to form a cumulative q g . gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the lm2747, and not in the mosfet itself. switching loss occurs during the brief transition period as the high-side mosfet turns on and off, during which both cur- rent and voltage are present in the channel of the mosfet. it can be approximated as: p sw =0.5xv in xi o x(t r +t f )xf sw where t r and t f are the rise and fall times of the mosfet. switching loss occurs in the high-side mosfet only. for this example, the maximum drain-to-source voltage ap- plied to either mosfet is 3.6v. the maximum drive voltage at the gate of the high-side mosfet is 3.1v, and the maxi- mum drive voltage for the low-side mosfet is 3.3v. due to the low drive voltages in this example, a mosfet that turns on fully with 3.1v of gate drive is needed. for designs of 5a and under, dual mosfets in so-8 provide a good trade-off between size, cost, and efficiency. support components c in 2 - a small (0.1 to 1 f) ceramic capacitor should be placed as close as possible to the drain of the high-side mosfet and source of the low-side mosfet (dual mos- fets make this easy). this capacitor should be x5r type dielectric or better. r cc ,c cc - these are standard filter components designed to ensure smooth dc voltage for the chip supply. r cc should be1to10 ? .c cc should 1 f, x5r type or better. c boot - bootstrap capacitor, typically 100 nf. r pull-up ? this is a standard pull-up resistor for the open- drain power good signal (pwgd). the recommended value is 100 k ? connected to v cc . if this feature is not necessary, the resistor can be omitted. d 1 - a small schottky diode should be used for the bootstrap. it allows for a minimum drop for both high and low-side drivers. the mbr0520 or bat54 work well in most designs. r cs - resistor used to set the current limit. since the design calls for a peak current magnitude (i out + (0.5 x ? i out )) of 4.8a, a safe setting would be 6a. (this is below the satura- tion current of the output inductor, which is 7a.) following the equation from the current limit section, a 1.3 k ? resistor should be used. r fadj - this resistor is used to set the switching frequency of the chip. the resistor value is approximated from the fre- quency vs frequency adjust resistor curve in the typical performance characteristics section. for 300 khz operation, a 100 k ? resistor should be used. c ss - the soft-start capacitor depends on the user require- ments and is calculated based on the equation given in the section titled start up/soft-start . therefore, fo ra7ms delay, a 12 nf capacitor is suitable. control loop compensation the lm2747 uses voltage-mode (?vm?) pwm control to cor- rect changes in output voltage due to line and load tran- sients. vm requires careful small signal compensation of the control loop for achieving high bandwidth and good phase margin. the control loop is comprised of two parts. the first is the power stage, which consists of the duty cycle modulator, output inductor, output capacitor, and load. the second part is the error amplifier, which for the lm2747 i sa9mhz op-amp used in the classic inverting configuration. figure 13 shows the regulator and control loop components. lm2747 www.national.com 15
application information (continued) one popular method for selecting the compensation compo- nents is to create bode plots of gain and phase for the power stage and error amplifier. combined, they make the overall bandwidth and phase margin of the regulator easy to see. software tools such as excel, mathcad, and matlab are useful for showing how changes in compensation or the power stage affect system gain and phase. the power stage modulator provides a dc gain a dc that is equal to the input voltage divided by the peak-to-peak value of the pwm ramp. this ramp is 1.0v pk-pk for the lm2747. the inductor and output capacitor create a double pole at frequency f dp , and the capacitor esr and capacitance cre- ate a single zero at frequency f esr . for this example, with v in = 3.3v, these quantities are: in the equation for f dp , the variable r l is the power stage resistance, and represents the inductor dcr plus the on resistance of the top power mosfet. r o is the output voltage divided by output current. the power stage transfer function g ps is given by the following equation, and figure 14 shows bode plots of the phase and gain in this example. a=lc o (r o +r c ) b=l+c o (r o r l +r o r c +r c r l ) c=r o +r l the double pole at 4.5 khz causes the phase to drop to approximately -130? at around 10 khz. the esr zero, at 20.3 khz, provides a +90? boost that prevents the phase from dropping to -180 o . if this loop were left uncompensated, the bandwidth would be approximately 10 khz and the phase margin 53?. in theory, the loop would be stable, but would suffer from poor dc regulation (due to the low dc gain) and would be slow to respond to load transients (due to the low bandwidth.) in practice, the loop could easily become unstable due to tolerances in the output inductor, capacitor, or changes in output current, or input voltage. therefore, the loop is compensated using the error amplifier and a few passive components. for this example, a type iii, or three-pole-two-zero approach gives optimal bandwidth and phase. in most voltage mode compensation schemes, including type iii, a single pole is placed at the origin to boost dc gain 20150964 figure 13. power stage and error amp 20150969 20150970 figure 14. power stage gain and phase lm2747 www.national.com 16
application information (continued) as high as possible. two zeroes f z1 and f z2 are placed at the double pole frequency to cancel the double pole phase lag. then, a pole, f p1 is placed at the frequency of the esr zero. a final pole f p2 is placed at one-half of the switching fre- quency. the gain of the error amplifier transfer function is selected to give the best bandwidth possible without violat- ing the nyquist stability criteria. in practice, a good crossover point is one-fifth of the switching frequency, or 60 khz for this example. the generic equation for the error amplifier transfer function is: in this equation the variable a ea is a ratio of the values of the capacitance and resistance of the compensation compo- nents, arranged as shown in figure 13 .a ea is selected to provide the desired bandwidth. a starting value of 80,000 for a ea should give a conservative bandwidth. increasing the value will increase the bandwidth, but will also decrease phase margin. designs with 45-60? are usually best because they represent a good trade-off between bandwidth and phase margin. in general, phase margin is lowest and gain highest (worst-case) for maximum input voltage and mini- mum output current. one method to select a ea is to use an iterative process beginning with these worst-case conditions. 1. increase a ea 2. check overall bandwidth and phase margin 3. change v in to minimum and recheck overall bandwidth and phase margin 4. change i o to maximum and recheck overall bandwidth and phase margin the process ends when the both bandwidth and the phase margin are sufficiently high. for this example input voltage can vary from 3.0 to 3.6v and output current can vary from 0 to 4a, and after a few iterations a moderate gain factor of 101db is used. the error amplifier of the lm2747 has a unity-gain band- width of 9 mhz. in order to model the effect of this limitation, the open-loop gain can be calculated as: the new error amplifier transfer function that takes into account unity-gain bandwidth is: the gain and phase of the error amplifier are shown in figure 15 . in vm regulators, the top feedback resistor r fb2 forms a part of the compensation. setting r fb2 to 10 k ? 1%, usually gives values for the other compensation resistors and ca- pacitors that fall within a reasonable range. (capacitances > 1 pf, resistances < 1m ? )c c1 ,c c2 ,c c3 ,r c1 , and r c2 are selected to provide the poles and zeroes at the desired frequencies, using the following equations: 20150974 20150975 figure 15. error amp. gain and phase lm2747 www.national.com 17
application information (continued) in practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest 10% capacitor values above what are suggested for c c1 and c c2 , the closest 10% capacitor value below the suggestion for c c3 , and the closest 1% resistor values below the sugges- tions for r c1 ,r c2 . note that if the suggested value for r c2 is less than 100 ? , it should be replaced by a short circuit. following this guideline, the compensation components will be: c c1 =27pf 10%, c c2 = 820 pf 10% c c3 = 2.7 nf 10%, r c1 = 39.2 k ? 1% r c2 = 2.55 k ? 1% the transfer function of the compensation block can be derived by considering the compensation components as impedance blocks z f and z i around an inverting op-amp: as with the generic equation, g ea-actual must be modified to take into account the limited bandwidth of the error ampli- fier. the result is: the total control loop transfer function h is equal to the power stage transfer function multiplied by the error amplifier transfer function. h=g ps xh ea the bandwidth and phase margin can be read graphically from bode plots of h ea as shown in figure 16 . the bandwidth of this example circuit is 59 khz, with a phase margin of 60?. efficiency calculations the following is a sample calculation. a reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the output power (p out ) loss and the total power (p total ) loss: the output power (p out ) for the typical application circuit design is (1.2v x 4a) = 4.8w. the total power (p total ), with an efficiency calculation to complement the design, is shown below. the majority of the power losses are due to the low side and high side mosfet?s losses. the losses in any mosfet are group of switching (p sw ) and conduction losses (p cnd ). p fet =p sw +p cnd = 61.38 mw + 270.42 mw p fet = 331.8 mw fet switching loss (p sw ) p sw =p sw(on) +p sw(off) p sw =0.5xv in xi out x(t r +t f )xf sw 20150985 20150986 figure 16. overall loop gain and phase lm2747 www.national.com 18
application information (continued) p sw =0.5x3.3vx4ax300khzx31ns p sw = 61.38 mw the fds6898a has a typical turn-on rise time t r and turn-off fall time t f of 15 ns and 16 ns, respectively. the switching losses for this type of dual n-channel mosfets are 0.061w. fet conduction loss (p cnd ) p cnd =p cnd1 +p cnd2 p cnd1 =i 2 out xr ds(on) xkxd p cnd2 =i 2 out xr ds(on) x k x (1-d) r ds(on) =13m ? and the factor is a constant value (k = 1.3) to account for the increasing r ds(on) of a fet due to heat- ing. p cnd1 = (4a) 2 x13m ? x 1.3 x 0.364 p cnd2 = (4a) 2 x13m ? x 1.3 x (1 - 0.364) p cnd = 98.42 mw + 172 mw = 270.42 mw there are few additional losses that are taken into account: ic operating loss (p ic) p ic =i q_vcc xv cc , where i q-vcc is the typical operating v cc current p ic = 1.7 ma x 3.3v = 5.61 mw fet gate charging loss (p gate ) p gate =nxv cc xq gs xf sw p gate =2x3.3vx3ncx300khz p gate = 5.94 mw the value n is the total number of fets used and q gs is the typical gate-source charge value, which is 3 nc. for the fds6898a the gate charging loss is 5.94 mw. input capacitor loss (p cap ) where, here n is the number of paralleled capacitors, esr is the equivalent series resistance of each, and p cap is the dissi- pation in each. so for example if we use only one input capacitor of 24 m ? . p cap = 88.8 mw output inductor loss (p ind ) p ind =i 2 out x dcr where dcr is the dc resistance. therefore, for example p ind = (4a) 2 x11m ? p ind = 176 mw total system efficiency p total =p fet +p ic +p gate +p cap +p ind lm2747 www.national.com 19
example circuits part part number type package description vendor u1 lm2747 synchronous controller tssop-14 nsc q1 fds6898a dual n-mosfet so-8 20v, 10 m ? @ 4.5v, 16nc fairchild d1 mbr0520lti schottky diode sod-123 l1 do3316p-472 inductor 4.7 h, 4.8arms 18 m ? coilcraft c in 1 16sp100m aluminum electrolytic 10mm x 6mm 100 f, 16v, 2.89arms sanyo c o 1 6sp220m aluminum electrolytic 10mm x 6mm 220 f, 6.3v 3.1arms sanyo c cc ,c boot, c in 2, c o 2 vj1206y104kxxa capacitor 1206 0.1 f, 10% vishay c c3 vj0805y332kxxa capacitor 0805 3300 pf, 10% vishay c ss vj0805a123kxaa capacitor 0805 12 nf, 10% vishay c c2 vj0805a821kxaa capacitor 0805 820 pf 10% vishay c c1 VJ0805A220KXAA capacitor 0805 22 pf, 10% vishay r fb2 crcw08051002f resistor 0805 10.0 k ? 1% vishay r fb1 crcw08054991f resistor 0805 4.99 k ? 1% vishay r fadj crcw08051003f resistor 0805 100 k ? 1% vishay r c2 crcw08052101f resistor 0805 2.1 k ? 1% vishay r cs crcw08052101f resistor 0805 2.1 k ? 1% vishay r cc crcw080510r0f resistor 0805 10.0 ? 1% vishay r c1 crcw08055492f resistor 0805 54.9 k ? 1% vishay r pull-up crcw08051003j resistor 0805 100 k ? 5% vishay c clk vj0805a560kxaa capacitor 0805 56 pf, 10% vishay 20150932 figure 17. 3.3v to 1.8v @ 2a, f sw = 300 khz lm2747 www.national.com 20
example circuits (continued) part part number type package description vendor u1 lm2747 synchronous controller tssop-14 nsc q1 fds6898a dual n-mosfet so-8 20v, 10 m ? @ 4.5v, 16 nc fairchild d1 mbr0520lti schottky diode sod-123 l1 do3316p-682 inductor 6.8 h, 4.4arms, 27 m ? coilcraft c in 1 16sp100m aluminum electrolytic 10mm x 6mm 100 f, 16v, 2.89arms sanyo c o 1 10sp56m aluminum electrolytic 6.3mm x 6mm 56 f, 10v 1.7arms sanyo c cc ,c boot, c in 2, c o 2 vj1206y104kxxa capacitor 1206 0.1 f, 10% vishay c c3 vj0805y182kxxa capacitor 0805 1800 pf, 10% vishay c ss vj0805a123kxaa capacitor 0805 12 nf, 10% vishay c c2 vj0805a821kxaa capacitor 0805 820 pf 10% vishay c c1 vj0805a330kxaa capacitor 0805 33 pf, 10% vishay r fb2 crcw08051002f resistor 0805 10.0 k ? 1% vishay r fb1 crcw08053161f resistor 0805 3.16 k ? 1% vishay r fadj crcw08051003f resistor 0805 100 k ? 1% vishay r c2 crcw08051301f resistor 0805 1.3 k ? 1% vishay r cs crcw08052101f resistor 0805 2.1 k ? 1% vishay r cc crcw080510r0f resistor 0805 10.0 ? 1% vishay r c1 crcw08053322f resistor 0805 33.2 k ? 1% vishay r pull-up crcw08051003j resistor 0805 100 k ? 5% vishay c clk vj0805a560kxaa capacitor 0805 56 pf, 10% vishay 20150933 figure 18. 5v to 2.5v @ 2a, f sw = 300 khz lm2747 www.national.com 21
example circuits (continued) part part number type package description vendor u1 lm2747 synchronous controller tssop-14 nsc q1 fds6898a dual n-mosfet so-8 20v, 10 m ? @ 4.5v, 16 nc fairchild d1 mbr0520lti schottky diode sod-123 l1 do3316p-332 inductor 3.3 h, 5.4arms 15 m ? coilcraft c in 1 16sp100m aluminum electrolytic 10mm x 6mm 100 f, 16v, 2.89arms sanyo c o 1 6sp220m aluminum electrolytic 10mm x 6mm 220 f, 6.3v 3.1arms sanyo c cc ,c boot, c in 2, c o 2 vj1206y104kxxa capacitor 1206 0.1 f, 10% vishay c c3 vj0805y222kxxa capacitor 0805 2200 pf, 10% vishay c ss vj0805a123kxaa capacitor 0805 12 nf, 10% vishay c c2 vj0805y332kxxa capacitor 0805 3300 pf 10% vishay c c1 vj0805a820kxaa capacitor 0805 82 pf, 10% vishay r fb2 crcw08051002f resistor 0805 10.0 k ? 1% vishay r fb1 crcw08052211f resistor 0805 2.21 k ? 1% vishay r fadj crcw08051003f resistor 0805 100 k ? 1% vishay r c2 crcw08052611f resistor 0805 2.61 k ? 1% vishay r cs crcw08054121f resistor 0805 4.12 k ? 1% vishay r cc crcw080510r0f resistor 0805 10.0 ? 1% vishay r c1 crcw08051272f resistor 0805 12.7k ? 1% vishay r pull-up crcw08051003j resistor 0805 100 k ? 5% vishay c clk vj0805a560kxaa capacitor 0805 56 pf, 10% vishay 20150934 figure 19. 12v to 3.3v @ 4a, f sw = 300khz lm2747 www.national.com 22
physical dimensions inches (millimeters) unless otherwise noted tssop-14 ns package number mtc14 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor manufactures products and uses packing materials that meet the provisions of the customer products stewardship specification (csp-9-111c2) and the banned substances and materials of interest specification (csp-9-111s2) and contain no ??banned substances?? as defined in csp-9-111s2. leadfree products are rohs compliant. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com lm2747 synchronous buck controller with pre-bias startup, and optional clock synchronization

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